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STLC1510
NorthenLiteTM G.lite DMT Transceiver
PRODUCT PREVIEW
s s s s s
ATM transport Forward Error correction & interleaving Framing & de-framing DMT modulation and demodulation Start-up & showtime control processing
LBGA132 ORDERING NUMBER: STLC1510
In addition, the STLC1510 provides the following features:
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Serial and Parallel network interface at backend to CO equipment Serial interface to the AFE chip STLC1511 Access to off chip memory Power-up boot program stored in ROM 132 balls 12x12x1.7 mm LBGA package Power Consumption: 0.75 Watt Power Supp.: 2.5 V (core) and 3.3 V (I/O ring) 1.0 GENERAL DESCRIPTION
The STLC1510 is a high-speed modem chip that provides the digital portion of a G.992.2 DSL access at a Central Office (CO) site. It provides downstream and upstream data transport between an ATM byte stream and an analog front-end chip using Discrete Multi-Tone (DMT) Modulation. The STLC1510 is compliant with ITU-T G.992.2 (G.Lite), G.996.1 (G.Test), G.994.1 (G.Handshake), G.997.1 (G.Ploam).
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Figure 1. Block Diagram
EN_D 950_E M U HP I_Data[7:0] 8 HP I_Addr[2:0] 3 ARM 2HP _IN T AR M_M ODE LinDr_A GC2 LinDr_AG C1
LinD r_Peak
H PI_RWN
HP I_CLK HP I_CSN
HP I_ASN
TxClk TxClav TxEnb TxSOC U TxData [7 :0 ] TxAddr[4:0 ] TxParity TxBP RxClk R xClav RxSOC URxData [ 7:0] RxAddr[4: 0] RxParity RxEnb
HPI DFE EPM
me m
m em m em
BPU
m em m em
FEC
MAP
pgm
NIF
TxSOUT[1 :0 ] A_SCLK CK35M RxSIN[1 : 0]
L AMB A Bus
7 7 REF_CLK
VDD3_3 VDD2_5 VSS
TAP
2 2 8
T GB
ctrl
AR M
D95 0
Dual MAC
SPI_ CLK SPI_ ENB
14
SPI_ DTX SPI_ DRX
TD I
Pmode[1:0]
C Mode[1:0]
D 950_CMO DE
TCK
TM S
TRSTN
GP IO[7:0]
VDD_PLL
Guard_PLL
VS S_PLL
RES ETN
VCODC
TDO
INF_OUT
November 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
R E F_ O U T
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2.0 LIST OF MAIN BLOCKS
The STLC1510 G.lite DMT Transceiver is formed by the following blocks (refer to Figure 1.):
Timing Generation Block (TGB)
The timing generation block generates global clock and synchronization signals for the STLC1510. It uses the input clock signals to derive the main internal and output clock signals, as well as all synchronization pulses required to coordinate timing between the sub-blocks.
Embedded Processor Module (EPM)
The EPM includes two embedded processor cores: the ARM7TDMI, a RISC microprocessor, and the D950, a 16-bit DSP processor. The RISC microprocessor handles the chip control, G.Lite start-up and showtime control and DSP initialization. It also implements the Framing and Interleaving/Deinterleaving function required by G.992.2 standard.
Test Access Port (TAP)
This block provides the test access to the STLC1510 using JTAG and BIST techniques.
HPI Interface Block Processing Unit (BPU)
Computationally intensive digital signal processing functions are performed in this engine. This engine utilizes customized DSP architecture that includes two multiplier/accumulator (MAC). A host processor interface is provided to allow the STLC1510 to be optionally controlled by an external microcontroller.
3.0 TRANSIENT ENERGY CAPABILITIES 3.1 ESD
ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM). The pins of the device are to be able to withstand minimum 2000V for the HBM.
Digital Front-End (DFE)
This block provides the interface to an external analog front-end (AFE) device. This block provides decimation, interpolation for the signal sample for the ADC and DAC on the AFE and signal level monitoring for the analog AGC.
3.2 Latch-up
Network Interface (NIF)
The NIF is a selectable interface that carries the ATM signals to and from the STLC1510. This interface supports one parallel interface (Utopia Level 2) or a serial data interface. The NIF includes a FIFO to buffer the data between the clock domains of the backend interface and the internal clock. The maximum sink or source current from any pin is limited to 200mA to prevent latch-up.
4.0 ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings, as specified below, are those ratings beyond which the device's lifetime may be impaired. The meeting of electrical specifications is not implied when the device is subjected to the absolute limits. The following table identifies the device's minimum and maximum ratings and along with the operatingconditions they define the limits for testing the device
Forward Error-Correction (FEC)
The Forward Error Correction is done using ReedSolomon Coding. The R-S FEC encoding is performed byte-wise in the transceiver on the transmitted bytes. The two basic parameters that determine the performance of the code are the code word size, which consists of one or more DMT symbols (S), and the number of redundant check bytes R.
Mapper/De-mapper Block (MAP)
The Mapper/De-mapper Block (MAP) performs the bit packing and un-packing and constellation encoder/decoder for a G.992.2 DSL modem. This block also supports generation of Reverb and medley.
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Table 1. ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD3_3 VDD2_5 Tamb VIN, VOUT VIN5 , VOUT5 IIN, IOUT PD Vesd I latchup
<1>
PARAMETER 3.3V Supply voltage w.r.t. VSS (0V) 2.5V Supply voltage w.r.t. VSS (0V) Ambient temperature Voltage at any 3.3V standard input or output Voltage at any 5V compatible input or output 1 Current at any input or outputs Power dissipation Electrostatic Protection I/O Latch-up Current V < 0V, V > Vdd
MINIMUM -0.5 -0.5 -40 -0.5 -0.8 -20 0 2000 200
MAXIMUM 4 3.3 85
VDD3_3 + 0.5
UNITS V V C V V mA W V mA
6.3 20 0.75
-0.8V undershoots and 6.3V overshoots do not last longer than 4nS.
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Figure 2. Ball Map.
STLC1510 Netlist
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STLC1510
Table 2. Pad Description
Signal Clock Interface REF_CLK I 5V Tol CMOS input 17.168 MHz or 35.328 MHz reference clock input.1 Hardware reset (active low) '1' - Normal operation '0' - Reduced REF_CLK frequency in bypass mode for chip test Power Mode Select Power Mode Select Clock Mode Select Clock Mode Select K13 I/O Pad Type Description BGA
RESETN D950_CMODE
I I
5V Tol CMOS input 5V Tol CMOS input
E13 C13
PMode_1 PMode_0 CMode_1 CMode_0
I I I I
5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input
G1 H1 H2 L1
STLC1511 AFE Interface A_SCLK CK35M RxSIN_1 RxSIN_0 TxSOUT_1 TxSOUT_0 SPI_CLK SPI_ENB SPI_DTX SPI_DRX XTAL_CTRL I O I I O O O O O I O 5V Tol CMOS input 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input 5V Tol CMOS input 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input 5V Tol 3.3V TTL 2mA slew ltd output ADC/DAC sample frame clock 35.328 MHz reference clock output. ADC serial input data ADC serial input data DAC serial output data DAC serial output data STLC1511 control interface clock TX/RX STLC1511 Enable Control signal TX STLC1511 Control Data RX STLC1511 input Control Data XTAL output control pin H14 J14 L14 K14 F14 E14 M14 M13 N14 L13 Not on BGA
STLC1512 Line Driver Interface LinDr_AGC1 LinDr_AGC2 LinDr_Peak O O O 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output STLC1511 AGC Gain control 1 STLC1511 AGC Gain control 2 STLC1511 Peak control2 D13 D14 C14
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Table 2. Pad Description
Signal Test Interface TCK TMS TDI TDO TRSTN I I I O I 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output dedicated TAP reset (active low) N9 N7 P8 N8 P9 I/O Pad Type Description BGA
Network Interface (UTOPIA / Serial Clock & Data) TxClk TxClav TxBP TxEnb TxSOC UTxData_7 UTxData_6 UTxData_5 UTxData_4 UTxData_3 UTxData_2 UTxData_1 UTxData_0 TxAddr_4 TxAddr_3 TxAddr_2 TxAddr_1 TxAddr_0 TxParity RxClk I/O O O I I I I I I I I I I I I I I I I I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol. CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol CMOS input 5V Tol. CMOS input 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output Input Utopia2 Tx clock or output PSIF Tx clock. Tx cell available signal. Tx back pressure signal. Tx Enable. Tx start of Cell Utopia2 Transmit data bit 7 Utopia2 Transmit data bit 6 Utopia2 Transmit data bit 5 Utopia2 Transmit data bit 4 Utopia2 Transmit data bit 3 Utopia2 Transmit data bit 2 Utopia2 Transmit data bit 1 Utopia2 Transmit data bit 0; also CDIF input data Utopia2 Transmit Address Utopia2 Transmit Address Utopia2 Transmit Address Utopia2 Transmit Address Utopia2 Transmit Address Odd parity bit of the data on UTxData[7:0]. Input Utopia2 Rx clock or output PSIF Rx clock. A4 B5 B4 A6 C2 G2 F2 F1 E1 E2 D2 D1 C1 B1 A1 A2 A3 B2 B3 N6
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Table 2. Pad Description
Signal RxClav RxEnb RxSOC URxData_7 URxData_6 URxData_5 URxData_4 URxData_3 URxData_2 URxData_1 URxData_0 RxAddr_4 RxAddr_3 RxAddr_2 RxAddr_1 RxAddr_0 RxParity HPI HPI_Data_7 HPI_Data_6 HPI_Data_5 HPI_Data_4 HPI_Data_3 I/O I/O I/O I/O I/O 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output HPI Port Data HPI Port Data HPI Port Data HPI Port Data HPI Port Data B14 A14 B13 A13 B12 I/O O I O O O O O O O O O I I I I I O Pad Type 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol. CMOS input 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol 3.3V TTL 2mA slew ltd output Description Rx cell available signal. Rx Enable. Rx start of Cell Utopia2 Receive data bit 7 Utopia2 Receive data bit 6 Utopia2 Receive data bit 5 Utopia2 Receive data bit 4 Utopia2 Receive data bit 3 Utopia2 Receive data bit 2 Utopia2 Receive data bit 1 Utopia2 Receive data bit 0; also CDIF output data Utopia2 Receive Address Utopia2 Receive Address Utopia2 Receive Address Utopia2 Receive Address Utopia2 Receive Address Odd parity bit of the data on URxData[7:0]. BGA P5 N4 P4 N3 P3 P2 N2 M2 P1 N1 M1 L2 K2 K1 J2 J1 N5
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Table 2. Pad Description
Signal HPI_Data_2 HPI_Data_1 HPI_Data_0 HPI_Addr_2 HPI_Addr_1 HPI_Addr_0 HPI_CLK HPI_RWN HPI_CSN HPI_ASN ARM2HP_INT I/O I/O I/O I/O I I I I I I I O Pad Type 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input/ 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol. CMOS input 5V Tol 3.3V TTL 2mA slew ltd output Description HPI Port Data HPI Port Data HPI Port Data HPI Port Address HPI Port Address HPI Port Address HPI Clock Input HPI Port Read/WriteN HPI Port Chip Select HPI Port Address Strobe Input Active-low ARM7 To Host Processor Interrupt3 BGA A12 A11 B11 B7 A7 B8 B9 B10 A8 A10 A9
Misc VCODC REF_OUT INF_OUT
EN_D950_EMU
I O O I
Analog Input 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input
VCO control voltage for stand alone PLL testing PLL REF signal at input to phase detector PLL INF signal at input to phase detector EN_D950_EMU=0; D950 core held in reset by ARM7, GPIO pin #1,2,3 and 4 are normal mode EN_D950_EMU=1; D950 core is not held in reset by ARM7, GPIO pins #1,2,3 and 4 are dedicated to the D950 emulator ARM_MODE=0; Connects external TAP pins directly to ARM_TAP ARM_MODE=1; ARM_TAP in daisy chain configuration after MTAP (i.e. same as ALPHA configuration) General Purpose I/O Ports General Purpose I/O Ports General Purpose I/O Ports
P6 J13 H13 P7
ARM_MODE
I
5V Tol CMOS input
P10
GPIO_7 GPIO_6 GPIO_5
I/O I/O I/O
5V Tol CMOS input /5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input / 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input / 5V Tol 3.3V TTL 2mA slew ltd output
N13 P14 P13
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Table 2. Pad Description
Signal GPIO_4 GPIO_3 GPIO_2 GPIO_1 GPIO_0 Power Supply VDD3_3_8 VDD3_3_7 VDD3_3_6 VDD3_3_5 VDD3_3_4 VDD3_3_3 VDD3_3_2 VDD3_3_1 VDD2_5_8 VDD2_5_7 VDD2_5_6 VDD2_5_5 VDD2_5_4 VDD2_5_3 VDD2_5_2 VDD2_5_1 VSS_20 VSS_19 VSS_18 VSS_17 P P P P P P P P P P P P P P P P P P P P 3.3 volt supply pad 3.3 volt supply pad 3.3 volt supply pad 3.3 volt supply pad 3.3 volt supply pad 3.3 volt supply pad 3.3 volt supply pad 3.3 volt supply pad 2.5 volt supply pad 2.5 volt supply pad 2.5 volt supply pad 2.5 volt supply pad 2.5 volt supply pad 2.5 volt supply pad 2.5 volt supply pad 2.5 volt supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad 3.3V I/O power supply 3.3V I/O power supply 3.3V I/O power supply 3.3V I/O power supply 3.3V I/O power supply 3.3V I/O power supply 3.3V I/O power supply 3.3V I/O power supply 2.5V ASIC core power supply 2.5V ASIC core power supply 2.5V ASIC core power supply 2.5V ASIC core power supply 2.5V ASIC core power supply 2.5V ASIC core power supply 2.5V ASIC core power supply 2.5V ASIC core power supply Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 D3 C5 C3 C4 L12 M12 K12 M11 M3 L3 K3 C10 C11 C12 D12 M4 C9 J3 J12 H12 I/O I/O I/O I/O I/O I/O Pad Type 5V Tol CMOS input / 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input / 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input /5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input / 5V Tol 3.3V TTL 2mA slew ltd output 5V Tol CMOS input / 5V Tol 3.3V TTL 2mA slew ltd output Description General Purpose I/O Ports/ D950_IDLE General Purpose I/O Ports/ D950_SNAP General Purpose I/O Ports/ D950_INCYCLE General Purpose I/O Ports/ D950_NERQ General Purpose I/O Ports/LCLK BGA N12 P12 N11 P11 N10
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Table 2. Pad Description
Signal VSS_16 VSS_15 VSS_14 VSS_13 VSS_12 VSS_11 VSS_10 VSS_9 VSS_8 VSS_7 VSS_6 VSS_5 VSS_4 VSS_3 VSS_2 VSS_1 VDD_PLL VSS_PLL Guard_PLL
<1> <2> <3>
I/O P P P P P P P P P P P P P P P P P P P
Pad Type common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad common ground supply pad 2.5 volt supply pad ground pad ground pad
Description Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 Ground return for VDD3_3 and VDD2_5 2.5V supply for PLL Ground return for PLL Ground Voltage reference for PLL
BGA M6 M5 H3 M7 G3 F3 E3 M9 C6 C7 C8 M10 E12 F12 M8 G12 G14 F13 G13
212 MHz in PLL bypass mode This pad is configured as a pseudo open drain connection and can only pull the output low, or go high impedance Add pullup to this pin on board. This pad is configured as a pseudo open drain connection and can only pull the output low, or go high impedance
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5.0 MAIN BLOCK DESCRIPTION
The following sections describe the sequence of functions performed by the chip
5.1.2 External Interface (Pins)
The STLC1510 connects to the ATM network via 37 external pins. These are illustrated in Figure 3. Note that the pins TxClk and RxClk are bidirectional and, along with UTxData[0] and URxData[0], are shared between the CDIF and U2PHY
5.1 Network Interface and Controller (NIF)
The Network Interface and Controller block (NIF) is responsible for transferring data between the STLC1510 and the ATM network. The NIF has two interfaces to the backplane: an 8-bit Utopia Level 2 Physical Interface (U2PHY) and a clock and data serial interface (CDIF). It communicates with the rest of the STLC1510 via the Lamba Bus. Figure 3. shows a functional/data path block diagram of the NIF (this diagram does not include all glue logic between the major functional blocks). 37 external pins are required for the U2PHY and CDIF interfaces (19 for the Tx direction, 18 for Rx). Pins are shared between the two interfaces, as they will not both be active at the same time.
5.1.3 Clock and data serial Interface (CDIF)
The STLC1510 can communicate serially to an ATM network through the CDIF. Two serial data lines, one for the Tx path (CO to CPE), the other for the Rx path (CPE to CO), and two respective clocks realize the exchange of information and control signals between the STLC1510 and the network. The CDIF of the STLC1510 has the following attributes:
s s
Synchronizes to the ATM network. Provides Tx and Rx clocks to the ATM network.
5.1.1 Features
s s
Transfers data between the ATM network and the STLC1510's Lamba Bus
s
Utopia Level 2 8-bit parallel interface. Up to 9 ATM cells (477 bytes) of rate adaptation buffering for the Utopia Level 2 TX interface. The amount of buffering is programmable via a memory-mapped register. Up to 2 ATM cells (106 bytes) of rate adaptation buffering for the Utopia Level 2 RX interface. The amount of buffering is programmable via a memory-mapped register. ATM Transconvergance (TC) layer cell processor with 16-bit data path: performs scrambling/descrambling, HEC calculation, cell delineation with error detection (no error correction) and cell rate decoupling by idle cell insertion/detection. Clock and Data serial interface. Implemented as a hardware module on the Lamba bus with an 8-bit data interface and 16bit control interface. 4 ATM cells (212 bytes) of rate adaptation buffering in each direction (TX and RX) for interfacing to the Lamba bus. Pads partial or runt cells (ATM cells of length less than 53 bytes) to 53 bytes in the TX direction to prevent loss of synchronization at the CPE.
Accepts idle ATM cells inserted by the ATM network in the Tx direction. These idle cells are used by the ATM network to adapt to the clock provided to it by the STLC1510. Generates clock gapping in the Tx direction. This serves two purposes: it is a flow control mechanism to the ATM network chip, and it can be used for the byte alignment. In the bytealignment role, a clock gap longer than a pre-set threshold indicates that the most significant bit of a byte should be transmitted on the next rising clock edge. This is useful for aligning data bytes to the overhead bits inserted by the STLC1510. In the flow control role, incoming data is not sampled when the clock is off. The threshold used to distinguish between byte alignment and flow control clock gapping is software programmable and has a range of from 0 to 65535 clock cycles (a 16 bit register stores the value). Generates clock gapping in the Rx direction. This serves as a flow-control mechanism; when there is no data available for transmission to the backplane, the clock is shut off, ensuring that no invalid data bits are sampled by the backplane.
s
s
s
s s
s
s
s
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Figure 3. NIF Off-Chip Signals
TxClk
CDIF TX
RxClk
CDIF RX
UTxData[0]
URxData[0]
UTxData[7:1]
8
URxData[7:1] U2PHY TX RxEnb RxSOC
8
U2PHY RX
TxEnb TxSOC TxAddr[4:0] TxClav TxBP TxParity 5
RxAddr[4:0] RxClav RxParity
5
The following tasks are performed by the ATM network (in accordance with ITU-T Recommendation I.432.1), and therefore do not have to be implemented in the STLC1510 when using the CDIF:
s s s
5.1.4 UTOPIA Level 2 Interface and Controller
The Universal Test and Operations Physical Interface for ATM (UTOPIA) provides a standard that links ATM layer or various management entities with a variety of physical (PHY) layers. The UTOPIA IF has the following features:
s s s
HCS generation (Tx). Payload scrambling (Tx). Optionally, enables clear channel mode, in which HCS generation and payload scrambling are disabled (Tx). HCS cell delineation (Rx). Payload descrambling (Rx). Idle cell filtering (Rx). Header error detection to recover valid ATM cells (header correction is not implemented) (Rx). Optionally, enables clear channel mode, in which every 53 x 8 = 424 bits are collected by the receiver and sent to the backplane (Rx).
s s
provides clock decoupling mechanism. throttles data flow from the ATM layer. indicates to the ATM layer when the modem is ready to receive data. signals to the ATM layer the presence of valid data for transmission. Recognizes the address when the modem is selected for communication. Supports octet-level and/or cell-level handshaking. UTOPIA Level 2 supports a multi-PHY operation for up to n PHY devices where, n=< 8 at ATM layers intended for 155 Mbps;
s s s s
s
s
s
s
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s s
n=< 4 at ATM layers intended for 622 Mbps. This interface is subdivided into two parts: the Transmit Interface (TxIF) and the Receive Interface (RxIF). Both the TxIF and RxIF are controlled by the ATM layer. The ATM layer provides an interface clock to the PHY layer for synchronizing all interface transfers. The PHY layer will incorporate rate-matching buffers. Transmit data is transferred from the ATM layer to the PHY layer as follows: first, the PHY layer indicates it can accept data, then the ATM layer drives data onto the data bus and asserts the TxEnb. The data flow is controlled by the PHY layer.
s s
first. Cell delineation is performed using a coding law checking the HEC field in the cell header according to the algorithm described in ITU-T Recommendation I.432. Error detection is performed as defined in ITU-T Recommendation I.432 with the exception that any HEC error is considered a multiple-bit error. Therefore, HEC error correction is not performed. The ATU-C transmitter preserves V-C and T-R interface byte boundaries (explicitly present or implied by ATM cell boundaries) at the U-C interface. Interfaces to the Lamba bus.
s
s
s
s
s
s
s
5.2 FIFO
For a complete definition of TxIF signals and RxIF signals please consult the UTOPIA Level 1 and UTOPIA Level 2 documents released by The ATM Forum Technical Committee. There is an additional signal added to the Utopia Interface in the TX direction: Back Pressure (TxBP). This signal alerts the backplane when a software programmable depth has been reached in the TX Utopia FIFO, while still allowing more data (up to the 10 cells maximum) to be accepted by the FIFO. The STLC1510 incorporates 4 FIFO buffers for rate decoupling:
s
Utopia TX FIFO (8 bit input from the Utopia TX interface, 16 bit output to the ATM-TC cell processor): 243 words X 16 bits/word = 486 bytes >= 9 ATM cells @ 53 bytes/cell Utopia RX FIFO (16 bit input from the ATM-TC cell processor, 8 bit output to the Utopia RX interface): 54 words X 16 bits/word = 108 bytes >= 2 ATM cells @ 53 bytes/cell Lamba TX FIFO (16 bit input from the ATM-TC cell processor, 8 bit output to the Lamba Bus): 106 words X 16 bits/word = 212 bytes >= 4 ATM cells @ 53 bytes/cell Lamba RX FIFO (8 bit input from the Lamba Bus, 16 bit output to the ATM-TC cell processor): 106 words X 16 bits/word = 212 bytes >= 4 ATM cells @ 53 bytes/cell All the FIFO's share the following features: Perform 8-bit to 16-bit word conversion or 16-bit to 8-bit word conversion, with storage implemented as 16-bit wide dual port RAMs. Flags indicating when the FIFO is full, almost full, empty, almost empty and half empty. (The FIFO depths for the almost full and almost empty flags are hard-wired). Diagnostic input and an error flag. The Utopia Tx FIFO has the following additional attributes:
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s
5.1.5 ATM Transport Convergence (TC) Layer Processor
The Cell TC block has the following attributes:
s s
Idle cells inserted in the Tx direction for cell rate de-coupling are discarded. HEC bytes are generated in the Tx direction as described in ITU-T Recommendation I.432, including the recommended modulo-2 addition (XOR) of the pattern binary 01010101 to the HEC bits. Scrambling of the cell payload is used in the transmit direction to improve the security and robustness of the HEC cell delineation mechanism. The cell payload is descrambled by the Cell TC block of an ATU receiver. When interfacing ATM bytes to the bearer channel, the most significant bit (msb) is sent
s s
s
s
s
s s
s
STLC1510
s
Software programmable generation of the flag TX_CLAV (CeLl AVailable, TX direction) via registers. This translates to the FIFO having a software programmable depth. Software programmable generation of the flag TX_BP (Back Pressure, TX direction) via registers. This allows the FIFO to throttle incoming data flow, while still accepting data that was already en route when the flag was asserted.
K F EC = S ( B + 1 )
and the RS Code Word length is
s
N F EC = K + R
The code word is transmitted over S DMT symbols, and hence the number of bytes per Data Frame is
The Utopia Rx FIFO has the following additional attributes:
s
N F EC R B' = -------------- = B + 1 + --S S
The Galois Field primitive element is defined by the zero of the primitive polynomial
Software programmable generation of the flag RX_CLAV (CeLl AVailable, RX direction) via registers. This translates to the FIFO having a software programmable depth.
p ( x) = x + x + x + x + 1
The Reed-Solomon generator polynomial is
8
4
3
2
5.3 Reed Solomon Forward Error Correction (RS-FEC)
Forward error correction is provided with byte-wise Reed Solomon (RS) Encoding and Decoding in a 256 element Galois Field.
R-1
G ( x) =
(x +
k=0
k
)
The RS encoder does not introduce latency. RS decoding has a latency of at least N , whereby the upper bound of the latency is given by the actual decoder implementation. The transmitter and receiver provide synchronization of the RS Code Words.
5.3.1 Parameters
The following parameter values for S and R are supported:
s s
5.4 Bit Mapper/Demapper Module (MAP) R = 0, 4, 8, 16 S = 1, 2, 4, 8, 16 RS is integer, 5.4.1 Features
s
Furthermore
s s s
G.992.2 Compliant constellation encoder, up to 15 bits per sub-carrier capability. Support for 1-bit per sub-carrier modulation (BAM) and idle sub-carriers. Constellation encoder, Q1.15 complex fixed point output. Bit unpacking and packing from/to 256-byte data frame. Support for pilot tone insertion. Support for REVERB, SEGUE and MEDLEY generation. Support for random 4-QAM generation. No trellis coding. Implemented as a peripheral device.
the combination S > 1 and D = 1 is allowed, while not required. byte wise coding over G F ( 256) , and hence N F EC 255 .
s
s s
s
The Reed-Solomon Code Word length is NF EC , and its value results from the selection of S and R , and the number of data bytes B per Data Frame, whereby
s s
B = 2...48...144
for
downstream,
or
s s s
B = 1...16...60 for upstream. The RS Data Word
length is
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STLC1510
5.4.2 Mapper Description
The mapper realizes the bit extraction and constellation encoding functions specified in G.922.2 ( 7.8.1 and 7.8.2 respectively); it is mainly intended to accelerate the main CPU in these bit manipulation operations. The mapper consists of:
s
5.5 Embedded Processor Core - Functional Description
The Embedded Processor Core consists of two programmable cores; the ARM7TDMI 32-bit microprocessor and the D950 16-bit DSP, their associated peripherals/memory, a DPCOMM (Dual-Port Communications) for messaging, and a Bridge/Arbiter/ Decode (BAD) block. A block diagram of the EPM is shown below. There are two buses locally used by the ARM7 core which are collectively known as the Advanced Microcontroller Bus Architecture (AMBA):
s s
A Bit Unpack unit, extracting a variable length bit string from the frame RAM A Constellation Encoder, converting the bits to a constellation point Pseudo -random sequence generators PRBS, & MAPPRG.
s
s
5.4.3 Demapper Description
The demapper consists of:
s
Advanced System Bus (ASB) Advanced Peripheral Bus (APB) connected to the ASB via an APB Bridge
A Constellation Decoder, converting the input constellation point to bits. A Bit Pack unit, inserting the variable length bit string into the frame RAM.
s
The LAMBA Bus, a subset of the AMBA bus specification, connects all the blocks in the data pump portion of the STLC1510.
Figure 4. EPM and LAMBA Bus Block Diagram
EP M
ASB can ex tend to the APB, X Bus , Y Bus, P Bus and LAM BA Bus . X Bus can extend to LAMB A Bus.
Bridge / Arbiter/ Dec od e
LA MBA BUS
16
X BUS A PB Y BUS P BUS Int Cntl APB Tmr B ridg e
DPCO MM
D ec
Xm em ASB Ym em
D950 CORE
ARM7 CORE
EMU TAP
B oot R OM
M em
D ec
H PI I/F
Pm em
Off Chip
Int T mr D ec C trl
EM U
TAP
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STLC1510
5.5.1 EPM Attributes
s
5.6 D950 DSP Core
The D950 core is a 16-bit DSP based on the Harvard architecture with three bidirectional 16-bit buses, two for data and one for instruction. Each of these buses is dedicated to a unidirectional 16-bit address bus (XA/YA/IA). The core is composed of three main units, a Data Calculation Unit (DCU), an Address Calculation Unit (ACU) and a Program Control Unit (PCU). Attributes
s s s s s
It provides access to internal registers for control and monitoring of the various hardware blocks. Provides control to perform Software (SW) download into the EPM and BPU memories as part of the power up sequence. Provides interrupt and exception handling for various macro blocks. Software on the EPM preforms several DSP functions that are not implemented in the BPU during Start-up, fast re-train or Show Time. Address space is large enough to address the internal registers, on-chip and some off-chip memories Provides debugging access through a JTAG interface, for SW running on the processor. Provides a dual port RAM to pass messages between the D950 and ARM7 cores. Supports an external Host Processor Interface to pass messages to/from the ARM7 Both cores have embedded emulator blocks for debug
s
s
s
Data Calculation Unit Address Calculation Unit Program Control Unit 16x16 single cycle MAC fast and flexible buses
s
s
s
The D950 top level consists of a D950 core, I mem, X mem1 (8 bit), X mem2 (16 bit), Y mem, Timer, Emulator, Interrupt Controller and TAP peripherals.
5.6.1 BAD - Bridge, Arbiter, Decoder
The Bridge/Arbiter/Decoder (BAD) block controls the data traffic among the ARM7, the D950 and the data pump. It provides decoding circuitry, LAMBA bus arbitration and isolation buffers.
s
s
5.5.2 ARM7TDMI MCU Core
The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors. The architecture is based on the Reduced Instruction Set Computer (RISC) principle which results in high instruction throughput and fast real-time interrupt response. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. While one instruction is being executed, the next is being decoded while the next is being fetched from memory. Attributes:
s s s s s s
5.6.2 DPCOMM - Dual Port RAM Messaging between ARM and D950
A Dual Port SRAM (1024x16) plus control registers, is connected between the APB bus of the ARM7 and the X bus of the D950. It is used as a mailbox to pass data between the ARM and the D950 DSP.
5.7 Host Processor Interface (HPI)
s
32-bit register bank 32-bit ALU 32-bit shifter 32-bit addressing 32x8 DSP multiplier "Thumb" architectural extension which allows generation of more memory efficient code Peripherals include decoders, timer and interrupt controller
s s
The HPI resides on the APB bus of the ARM7. The chip select for the HPI is generated by the APB Bridge. Since the HPI resides on the APB, it is treated as a 16 bit entity. This means that APB Address 0 is ignored and all HPI addresses are on 16 bit boundaries. i.e. incremental address location are h0000 h0002 h0004 etc... The HPI is dual port SRAM based with control that generates an interrupt when a message wants to be passed. The DPSRAM is implemented on-chip. External to the ASIC, the pins of this interface are 8 bidirectional data pins, 3 input address pins, 1 input Read/Writen pin, 1 Address Strobe, 1 clock, 1 input chip select pin and 1 output interrupt pin.
s
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STLC1510
s
A status register, an index register (for the Host Processor), an interrupt mask register, and a message buffer are required for both input and output transactions. The Input Status Register (ISR) is set by the Host Processor by writing h01 and cleared by writing h00 to the location. It is cleared by ARM by writing anything to it. The Output Status Registers (OSR) is set by the ARM by writing h01 and cleared by writing h00. It is cleared by the Host Processor by writing anything to it. The Input and Output Index Registers (IIR & OIR respectively) are reset to their starting value by writing h00 to their respective addresses. They can also be cleared by the Host Processor by writing anything to them. The Input Interrupt Mask Register (IIM) resets to h00, causing the Mask to be set (active low). This means that before the ARM can receive message ready interrupts from the Host Processor, this register must be written with
h0001 (by ARM) to unmask the interrupt.
s
s
The Output Interrupt Mask Register (OIM) resets to h00, causing the Mask to be set (active low). This means that before the Host Processor can receive message ready interrupts from the ARM, this register must be written with h01 (by the Host Processor) to unmask the interrupt. The Input and Output Message buffers are each 256 bytes long and 1 byte wide (an overflow in the index register will not write to the other message buffer, but will start to overwrite the current message buffer). Addressing of the Input and Output Message Buffers by the Host Processor is implemented indirectly via the Input and Output Index Registers. An external interrupt signal is generated when the output status register is set by the ARM7. An ARM7 interrupt signal is generated when the input status register is set by the Host Processor.
s
s
s
s
s
s
Figure 5. HPI Block Diagram
To /F ro m ARM
B C LK
Inp u t In t M ask O u tput S tatus R e g
To /F ro m HPI
BR ESn
2 56 B ytes O u tput Me ssa ge Buffer
PS EL _ H PI PW R ITE PE N AB L E PA D D R [1 0:1 ] PD _W [7 :0] PD _R [1 5 :0]
S AL PA BV E
AR M 2H P_ INT
R e a d/W rite R ea d
H PI_C SN Read R e ad /W rite H PI_R W N
2 5 6 Bytes Inp u t M essa g e Bu ffer O utp u t Int M a sk O utp u t In d e x R e g In pu t In de x R eg In p ut Sta tus R e g
C HN PT R L
H PI_A SN H PI_A D D R [2:0] H PI_D ATA_ IN [7:0] H P I_D ATA_O U T[7 :0 ] H P I_D ATA_O EN
H P I2AR M_ IN T
H PI_C L K
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STLC1510
5.7.1 Send Message from Host Processor to ARM
s
increment by 1 and access another byte location.
s
Read Input Status Register. If h01, the ARM has not read out the last message. If h00, the ARM has read the last message and the Input Message Buffer is available for use. Clear Input Index Reg by writing any value to its address (b'100).
Write message into Input Message Buffer by consecutively writing to its address (b'111). Each write will cause the Input Index Register to increment by 1 and access another byte location.
Clear the Output Status Reg (address b'000) by writing any value (the ARM can clear the OSR by writing 0 to it). Send Message from ARM to Host Processor Read Output Status Register. If h0001, the HP has not read out the last message. If h0000, the HP has read the last message and the Output Message Buffer is available for use. Write message into Output Message Buffer. This buffer is directly addressable by the ARM. Write h0001 to Output Status Register to interrupt the HP
s s
s
s
s
s
s
Write h01 to Input Status Register (address b'011) to interrupt the ARM
5.7.2 Receive Message from ARM by Host Processor
After receiving interrupt from ARM:
s
5.7.3 Receive Message from Host Processor by ARM
After receiving interrupt from HP:
s
Clear Output Index Register (address b'001) by writing any value.
Read message from Output Message Buffer by consecutively reading from its address (b'110). Each read will cause the Output Index Register to
Read message from Input Message Buffer. This buffer is directly addressable by the ARM.
Clear the Input Status Reg by writing h0001 to its address (the HP can clear the ISR by writing 0 to it).
s
s
Table 3. Signal List
Name BRESn BCLK PSEL_HPI PADDR[10:1] PD_W[7:0] PD_R[15:0] PWRITE PENABLE HP2ARM_INT HPI_CLK HPI_CSN HPI_ASN HPI_RWN HPI_ADDR[2:0] HPI_DATA_IN [7:0] HPI_DATA_OUT [7:0] HPI_DATA_OEN ARM2HP_INT I/O I I I I I O I I O I I I I I I O O O Internal/ External Internal Internal Internal Internal Internal Internal Internal Internal Internal External External External External External External External External External I/F APB APB APB APB APB APB APB APB APB HP HP HP HP HP HP HP HP HP Description Active low master RESET ASB clock Active high block select from APB APB address [11:1] APB write data APB read data APB Write - Active high, Read - Active low APB enable signal for timing Interrupt from Host Processor to ARM Host Processor bus clock Active low select from Host Processor Address Strobe from Host Processor HP Read - Active high, Write - Active low Host Processor address Host Processor data in Host Processor data out Host Processor data output enable Interrupt from ARM to Host Processor
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STLC1510
Table 4. HPI Memory Map
Host Processor Addr BIN
5.8 Block Processing Unit (BPU) Functional Description 5.8.1 Block Processing Unit - Core
The BPU is a programmable Digital Signal Processor responsible for the bulk of the high rate signal processing required in the modem. This processor utilizes a dual multiply accumulate Arithmetic Unit (AU) and Very Long Instruction Word (VLIW) format to achieve high processing efficiencies. The BPU is designed to perform the following functions:
s s s
HPI Reg
Output Status Reg Output Index Reg Output Mask Reg Input Status Reg Input Index Reg Input Mask Reg Output Message Buffer Input Message Buffer
000 001 010 011 100 101 110 111
s s s s s s s s s
Finite Impulse Filters (FIR) (Infinite Impulse Response) IIR FFT/IFFT Compression/decompression for FFT/IFFT FDEQ Tx Gain SNR calculation - recursive average add/remove cyclic prefix Slicer Auto Correlation FDEQ update Digital AGC
Figure 6. BPU Core Block Diagram
MCU/DFE
DATA MEMORY INTERFACE
XDATA MEM (XDM)
CDATA MEM (CDM)
XPORT
CPORT
ARITHMETIC UNIT (AU) AU CONTROL
ST LC 1510 B US IN TE RFAC E
ADDRESS CALCULATION UNIT (ACU)
D FE INTER FACE
PROGRAM CONTROL UNIT (PCU) AU CONTROL PROGRAM
MEMORY ADDRESS
PROGRAM MEMORY DATA
PROGRAM MEMORY
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STLC1510
5.9 Digital Front End (DFE)
The Digital Front End (DFE) block contains dedicated hardware to map signals between the analog interface (AFE) and the BPU. The DFE block has the following features:
s s s
in CPE mode. This consists of a digital phase interpolator and a digital D/A convertor Two loopback modes are provided in this block. Various bypass modes are provided to allow observation and isolation of any block in the DFE for test purposes. Interface to the LAMBA Bus.
It performs part of the sampling rate conversion between the AFE sampling rate and the 2x symbol rate of the BPU. It provides the necessary digital hardware to implement an analog-based AGC. It provides the necessary buffering to provide DMT symbol alignment within the BPU. It provides the facilities to allow timing recovery
s
s
5.9.1 Application Description
Figure 7. shows the application of the various DFE components when used in a CO (network) and CPE (remote) applications.
s
s
Figure 7. DFE Application Diagram
S T L C 1 5 1 0 (C O )
P IF
2 .2 08 M H z 2 .2 08 M H z
S T L C 1 5 2 0 (C P E )
PD D ly
ADC
~ 4. 4 16 M H z 4 .41 6 M H z
D FE
~ 2. 208 M H z
RSM
2 .2 08 M H z
D FE IIR
B PU
C S D F IR
4.416 MHz
A n a lo g
F ilter
h as e I n t e rp o la
tor
In terp o la tin g D A C
C IC
IIR
2 .2 08 M H z
B PU
D o m a in
~4.416 MHz
2.2 0 8 M H z
552 kHz
55 2 kH z
F ilter
P
F ilter
1.1 0 4 M H z
RSM
o p tion al
5.9.2 Interface Description
The registers accessible by the EPM are:
s s s s s s s s s s s s s s s
Decimator oversampling ratio Decimator order. Various loopback and bypass modes. Number of bits transferred to the Aloha ASIC DAC. AFE control registers. ADC clip counter. RSM parameters such as time constant, peak detector thresholds, peak detector modes,
integrator initialization, and detector outputs. IIR coefficients. Predictor IIR filter coefficients. Frame synchronization buffer length Timing recovery (crystal) control word. Timing recovery dither level selection. CO/CPE mode selection. Phase interpolator parameters such as alpha, frequency error and frequency error gain. CO peak detector parameters such as set-up and hold delays, threshold, and slew rate.
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5 52 k H z
F IR
552 kHz
F IF O
C IC F ilter
ADC
D A C C IC
~ 2.208M H z
C IC
I n te rp C SD
F IF O
STLC1510
5.10 Timing Generation Block (TGB)
The timing and reset generation block generates the device's global clock and synchronization signals. It uses the input clock signal (35.328 or 17.664 MHz) to derive the main internal clock signals, as well as all synchronization pulses required to coordinate timing between the sub-blocks. It also synchronizes the external RESETN with the internal ASIC clock.
The PLL input source, and PLL bypass signals are decoded from the PMode[1:0] pins. The CMode[1:0] pins are configured to always provide an 8.8 MHz input to the PLL when the PLL is not in bypass mode. Thus a divide by 2 or 4 will be selected to divide down the 17 or 35 MHz input clock references to 8.8 MHz. When the PLL is to be bypassed, it is powered down, and the input reference is used to bypass the PLL output.
s
Requires off-chip power supervisor to supply 10ms power-on reset (may also require push button reset for test) and 5ms TRSTN (TAP reset). Reset initialization will begin when RESETN is de-asserted by the off-chip power supervisor. After 2 rising edges of 4.4MHz clock, ASIC_RESETn is de-asserted and the STLC1510 (minus the BPU and D950 cores) will come out of reset. The ARM7 will follow its boot procedure which at some point, will download program code to the BPU and D950 cores then release them individually from reset.
s
The CK35M signals are generated by dividing down the internal ASIC clock. A 3 bit memory mapped register is used to adjust the reset phase of the divide by 6 generator. This gives software control of the phase of the CK35M signal which interfaces to the AFE device. There is also a programmable "one shot" mode which is used to reset the phase of the CK35M in the event the interface cannot synchronously meet the timing requirements. The NIFTX_CLK and NIFRX_CLK are generated when the NIF is in clock and data mode, i.e. not utopia mode.
5.11 Test Access Port Functional Description
The IEEE 1149.1 compliant Test Access Port (TAP) serves three purposes:
s
TAP interface for both ASIC and board level testing RAMBIST interface for testing the embedded memories during ASIC level test. General Purpose I/O port for general and miscellaneous control and monitoring.
s
s
5.10.1RESET Structure
The RESET structure for the STLC1510 has the following requirements/attributes:
In addition to these functions, there are two sets of mode pins, PMODE[1:0], and CMODE[1:0] which are used to put the STLC1510 into various modes. The definition of these modes are given below, where the shaded rows indicate special modes not to be used in normal operations.
Table 5. Power Mode Pin Definition
PMODE[1:0] 00 01 10 11 Mode State Power Down Mode 0 Power Down Mode 1 Power Down Mode 2 Power Down Mode 3 Nothing is powered down. ARM7 is powered down. D950 is powered down. BPU processor is powered down Description
Table 6. Clock Mode Pin Definition
CMODE[1:0] 00 01 1X Div2 Normal Bypass Mode State Description Master clock is REFCLK divided by 2 and then multiplied by 24. The input REFCLK should be 17.664 MHz Master clock is REFCLK divided by 4 and then multiplied by 24. The input REFCLK should be 35.328 MHz Master clock is REFCLK
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STLC1510
5.11.1DFT Interfaces
The STLC1510 incorporates certain features (Design for Testability, DFT) to improve the coverage of the final production test. Certain pins are dedicated to this features, and should not be used during normal operation. The Test Interface pins need to be connected as follows:
Signal TCK TMS TDI TDO TRSTN BGA N9 N7 P8 N8 P9 Connected to Pull-Up Pull-Up Pull-Up open See "RESET Structure" on page 21.
to allow low speed control and monitoring of external signals via the LAMBA bus. The block diagram for this interface is shown in Figure 8. The GPIO has the following attributes:
s s
There are 8 GPIO pins. Each pin can be individually set to one of 4 modes: * Input mode: Input signals will be sampled with LAMBA bus clock and stored in GPIO_in register. * Output mode: The GPIO pin is driven with the state in the GPIO_out register. * Interrupt mode: The GPIO_int register is set when there is a negative transition detected on its corresponding GPIO pin. The logic level of each interrupt pin will as well be stored in the GPIO_in register. An interrupt condition on any of the GPIO pins will result in an interrupt to the D950. * Dedicated mode. The GPIO pin is configured to be its second function according to the Table below If the pin does not have a second function, it will be configured as an input pin. There is no external clock for the GPIO interface and as such no timing defined.
5.11.2General Purpose I/O (GPIO) Interface
s
The STLC1510 has a 8-bit General Purpose I/O port
Figure 8. GPIO Interface Block Diagram
GP IO[7:0]
L am ba B us
G PIO _state
GP IO_ int
G PIO_in
G PIO_out
L am ba B u s Interface (L B I)
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5.12 Processor Emulation
There are three programmable processors on the LAVA ASIC: an ARM microprocessor, a D950 Digital Signal Processor, and a custom DSP engine (BPU). All these are capable of JTAG based emulation with the following attributes:
s s s s
Program modification and resume.
6.0 ELECTRICAL CHARACTERISTICS
This device shall meet the functional requirements detailed herein when operated over the specified timing, electrical, and temperature range.
Stop on breakpoint. Single step Full register R/W.
7.0 OPERATING RANGES
The operating ranges shall be in accordance with the following table.
Table 7. Operating Ranges
SYMBOL VDD3_3 VDD2_5 IDD3 IDDS3 IDD2 IDDS2 TA TJ
<1>
PARAMETER CMOS 3.3v I/O Supply voltage CMOS 2.5v Core Supply voltage CMOS 3.3v I/O Supply current CMOS 3.3v I/O Static supply current CMOS 2.5v Core Supply current CMOS 2.5v Core Static supply current Ambient temperature under bias1 Operating junction temperature -40 -40 3.0
MIN.
NOM. 3.3 2.5 11 TBD 240 TBD 25 25
MAX. 3.6 2.75
UNITS V V mA mA mA mA xC xC
2.25
85 105
Assuming no air flow and a package thermal resistance of 30xC/watt
7.1 DC Characteristics
The following table identifies the general DC characteristics for input and output pins.
Table 8. General Interface Electrical Characteristics
SYMBOL Vil Vih Vol Voh Iil Iih Ioz Ipu Ipd Rup Rpd
<1> <2>
PARAMETER Low level i/p voltage High level i/p voltage Low level o/p voltage
1
Conditio ns
Min
Typ
Max 0.8
Unit V V
2.0 Iol = 2mA Ioh = 2mA Vi=0V Vi=VD3_3 Vi=VDD5 Vo=0V or VDD3_3 Vi = 0V Vi = VDD5 Vi = 0V Vi = VDD2_5 -50 100 50 50 2.4 1.0 2.0 4.0 1.0 0.4
V V A A A A A A k k
High level o/p voltagea Low Level Input Current without pull-up device2 High Level Input Current without pulldown deviceb Tri-state Output leakage without pull up/down deviceb Pullup current Pulldown current Equivalent pull-up resistance Equivalent pull-down resistance
Takes into account 0.075*Vdd voltage drop in both supply lines. The leakage currents are generally very small, < 1nA. The value given here, i A, is a maximum that can occur after an Electrostatic Stress on the pin.
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STLC1510
7.2 AC Characteristics 7.2.1 AFE Interface Timing Figure 9. AFE Data Interface Timing (TTL)
CK 35M
ta cc
T x SO U T [1 :0 ]
tse
th o
R x S IN [1 :0 ]
tse
th o
A S_CLK
Table 9. AFE Data Interface Timing
Pin Name TxSOUT[1:0] TxSIN[1:0] TxSIN[1:0] AS_CLK AS_CLK tacc tse tho tse tho Parameter 0 5ns 5ns 5ns 5ns Min. Max. 10ns Reference Pin w.r.t. rising CK35M w.r.t. rising CK35M w.r.t rising CK35M w.r.t. rising CK35M w.r.t rising CK35M
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Figure 10. AFE Control Interface Timing (TTL)
S P I_ C L K ta c c
SP I_ E N B
tac c
S P I_ D T X
tse
th o
S P I_ D R X
Table 10. AFE Control Interface Timing
Pin Name SPI_ENB SPI_DTX SPI_DRX SPI_DRX tacc tacc tse tho Parameter 0 0 5ns 5ns Min. Max. 5ns 5ns Reference Pin w.r.t. rising SPI_CLK w.r.t. rising SPI_CLK w.r.t. falling SPI_CLK w.r.t falling SPI_CLK
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Figure 11. Line Driver Control Interface Timing (TTL)
CK35M ta c c
L in D r _C T R L 1 L in D r _C T R L 2 L in D r _A G C
Table 11. Line Driver Control Interface Timing
Pin Name LinDr_CTRL1 LinDr_CTRL2 LinDr_AGC tacc tacc tacc Parameter 0 0 0 Min. Max. 7ns 7ns 7ns Reference Pin w.r.t. rising CK35M w.r.t. rising CK35M w.r.t. rising CK35M
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STLC1510
Figure 12. Test Interface Timing (TTL)
T CK
ta c c
TD O
tse
th o
T DI
tse
th o
T RST N
Table 12. Test Interface Timing
Pin Name TDO TDI TDI TRSTN TRSTN tacc tse tho tse tho Parameter 0 5ns 5ns 5ns 5ns Min. Max. 10ns Reference Pin w.r.t. rising TCK w.r.t. rising TCK w.r.t rising TCK w.r.t. rising TCK w.r.t rising TCK
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STLC1510
Network Interface Timing Figure 13. UTOPIA Transmit Interface Timing
T xC L K tac c
T x C la v
tse TxEn b T xS O C U T x D a ta [7 :0] T x A d d r[4:0 ] T x P ar ity
tho
Table 13. Transmit Utopia Interface Timing
Pin Name TxClav TxSOC TxSOC TxEnb TxEnb UTxData[7:0] UTxData[7:0] TxAddr[4:0] TxAddr[4:0] TxParity TxParity tacc tse tho tse tho tse tho tse tho tse tho Parameter 0 5ns 2ns 5ns 2ns 5ns 2ns 5ns 2ns 5ns 2ns Min. Max. 10ns Reference Pin w.r.t. rising TxClk w.r.t. rising TxClk w.r.t rising TxClk w.r.t. rising TxClk w.r.t rising TxClk w.r.t. rising TxClk w.r.t. rising TxClk w.r.t. rising TxClk w.r.t rising TxClk w.r.t. rising TxClk w.r.t rising TxClk
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Figure 14. UTOPIA Receive Interface Timing
R xC L K ta cc
R xC lav R xS O C U R xD ata[7 :0 ] R xParity tse tho
R xE n b R xA d dr[4 :0]
Table 14. Receive Utopia Interface Timing
Pin Name RxClav RxEnb RxEnb RxSOC URxData[7:0] RxAddr[4:0] RxAddr[4:0] RxParity tacc tse tho tacc tacc tse tho tacc Parameter 0 5ns 2ns 0 0 5ns 2ns 5ns 10ns 10ns Min. Max. 10ns Reference Pin w.r.t. rising RxClk w.r.t. rising RxClk w.r.t rising RxClk w.r.t. rising RxClk w.r.t rising RxClk w.r.t. rising RxClk w.r.t. rising RxClk w.r.t. rising RxClk
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Figure 15. Serial Transmit Interface Timing
T x C lk tse tho
U T xD a ta [0 ]
Table 15. Transmit Serial Interface Timing
Pin Name TxClk UTxData[0] UTxData[0] Parameter frequency tse tho 0ns 0ns w.r.t. rising TxClk w.r.t. rising TxClk Min. Max. Reference Pin
Figure 16. Serial Receive Interface Timing
R x C lk ta c c
U R xD a ta [0 ]
Table 16. Receive Serial Interface Timing
Pin Name RxClk URxData[0] Parameter frequency tacc 0 3ns w.r.t. falling RxClk Min. Max. Reference Pin
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Host Processor Interface Timing
Figure 17. Host Processor Interface Timing (TTL)
H PI_BS
ts e
th o
H P I_ A d dr [ 2 :0 ] H P I _ R W N ,H P I_ C SN H P I _ D a ta [ 7 :0 ]
tacc
H P I_ D a ta [7 :0 ]
Table 17. Host Processor Interface Timing
Pin Name HPI_Addr[2:0] HPI_Addr[2:0] HPI_CSN HPI_CSN HPI_RWN HPI_RWN HPI_Data[7:0] HPI_Data[7:0] HPI_Data[7:0] tse tho tse tho tse tho tse tho tacc Parameter Min. 2.45ns 0.01ns 3.1ns 0.01ns 0.84ns 0.01ns 2.15ns 0.01ns 10ns Max. Reference Pin w.r.t. rising HPI_BS w.r.t. rising HPI_BS w.r.t. rising HPI_BS w.r.t. rising HPI_BS w.r.t. rising HPI_BS w.r.t. rising HPI_BS w.r.t. rising HPI_BS w.r.t. falling HPI_CSN w.r.t. falling HPI_CSN
7.2.2 GPIO Interface Timing
The GPIO[7:0] pins are memory mapped programmable pins. These pins can be programmed as input or output providing visibility to internal chip access points, as well as an ability to latch external control signals. A special mode can be configured where the
LAMBA Bus Clock is made available on a configured output pin GPIO[0]. For timing characterization, this mode should be used to exercise the GPIO[7:1] pins as both inputs and outputs. The diagram below refers to this special mode.
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STLC1510
Figure 18. GPIO Interface Timing
G P IO [0] ta c c
G P IO [1:7 ]
tse
th o
G P IO [1 :7 ]
Table 18. GPIO Interface Timing
Pin Name GPIO[1:7] GPIO[1:7] GPIO[1:7] tacc tse tho Parameter 0 5ns 2ns Min. Max. 10ns Reference Pin w.r.t. rising GPIO[0] w.r.t. rising GPIO[0] w.r.t. rising GPIO[0]
7.3 Power-up supply sequencing
There are two power supply voltages that must be applied to this chip to ensure correct functionality, (3.3V and 2.5V). The chip itself will function correctly regardless of the sequence in which the supplies are applied on power-up. However if the 3.3V supply is off and there is external 5V activity at the IOs, the internal ESD protection circuitry will clamp the external signals at 2.8 Volts maximum (by sinking as much current as provided by the interface).
Figure 19. The NIF Serial Interface
TxCl k UTx Data[0] Ne twork Rx Clk UR xData [0 ] STLC1510
8.0 EXTERNAL INTERFACE TIMING 8.1 NIF (Network Interface) Serial Interface
The NIF serial interface consists of separate clock and data lines in the RX and TX directions. This interface is illustrated briefly in Figure 19.
In the Tx direction, the reception of a data byte from the network starts with the most significant bit. Bits are sampled by STLC1510 on the rising edge of TxClk. In the presence of clock gapping (which is generated by the STLC1510, as it supplies the clocks in both directions), a previous bit persists until the next rising edge of the clock. Figure 21. shows the relationship between TxClk and UTxData[0].
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STLC1510
Figure 20. Network Serial Interface Tx Timing
Tx Clk U T x Data[0 ] B (1 )
B(0 ) B(7 ) B( 6) B (5) B (4)
In the Rx direction, the most significant bit of a data byte is transmitted to the network first, with the least significant bit transmitted last. The serial data stream is sampled by the network on the rising edge of Rx-
Clk. Samples at the gapped positions are ignored. Figure 21. illustrates the Rx timing diagram of the serial interface. Ignored samples are indicated by 'X' in the timing diagram.
Figure 21. Network Serial Interface Rx Timing
Rx Clk UR x D ata[0]
B(1 ) B(0 ) X B (7 ) B(6 ) X X B(5 )
Figure 22. The NIF Utopia Level 2 Interface
8.2 UTOPIA Level 2 Interface
The Utopia Level 2 Interface is an 8-bit interface, operating independently in the TX and RX directions. The Utopia Level 2 Interface is briefly illustrated in Figure 22. General features:
s
Tx C lk U Tx Data[7:0] Tx A ddr[4:0] Tx E nb Tx S O C Tx P arity T x Clav T x BP N etw ork (ATM L ay er) S TLC 1510 (M PH Y L ay er)
Implemented according to The ATM Forum Technical Committee's Utopia Level 2 specification. Utopia Level 2 is an extension of Utopia Level 1 which provides for connecting multiple MPHY layer devices to a single ATM layer. Once a given MPHY layer device has been selected for data transfer according to the mechanisms specified in Utopia Level 2, the transfer itself is performed according to the mechanisms specified in Utopia Level 1. 8-bit data transfer in each direction (TX and RX), with a maximum clock speed of approximately 21 MHz. Clocks are provided by the ATM layer through the TxClk and RxClk ports. (ATM layer is the master, PHY layer is the slave) There are 5 address lines for each of the TX and RX interfaces. Up to 31 addresses are supported, with the 32nd address (11111) being a reserved, idle address. Single PHY operation is supported by leaving the address lines set to the address of the PHY device. For more information, please see the ATM
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R x Clk U R x Data[7:0] R xA ddr[4 :0] R x Enb RxSOC
s
s
s
R x P arity R x C la v
s
STLC1510
Forum Technical Committee's Utopia Level 1 and Utopia Level 2 specifications, and Chapter 7 of this document, Network Interface and Controller (NIF).
Features of MPHY Layer Cell-Level Handshake (Tx Direction):
s s
A single MPHY port at a time is selected for a cell transmission. However, another MPHY port may be polled for its TxClav status while the selected MPHY port transfers data. The ATM layer polls the TxClav status of a MPHY port by placing its address on TxAddr. The MPHY port (STLC1510 device) drives TxClav during each cycle following one with its address on the TxAddr lines.
The ATM layer selects a MPHY port for transfer by placing the desired MPHY address onto TxAddr, when TxEnb is deasserted (high) during the current clock cycle, and asserted (low) during the next clock cycle. All MPHY devices only examine the value on TxAddr for selection purposes when TxEnb is deasserted (high). The MPHY port is selected starting from the cycle after its address is on the TxAddr lines, and TxEnb is deasserted (high); and ending in the cycle a new MPHY port is addressed for selection, and TxEnb is deasserted (high).
Figure 23. depicts the polling phase and the selection phase of the UTOPIA2 transmit interface. After the selection of the MPHY port, the cell transfer is executed the same way as in UTOPIA Level 1.
Figure 23. UTOPIA Level 2 transmit timing, polling phase and selection phase.
se le ctio n
polling
po lling
T xClk
T xA dd r
1F
N -1
1F
N+3
1F
N +1
1F
N
1F
N+3
1F
N+1
1F
N -1
N+3
N N+1
N +3 N+1
T xClav
N -1
T xE nb
U T xD ata
P 40
P 41
P4 2
P 43
P 44
P 45
P 46
P 47
P 48
H1
H2
H3
H4
T xS OC
C ell trans m iss ion to: P HY N P H Y N +3
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STLC1510
The TxBP pin is not part of the Utopia Level 2 specification, but its functionality does not interfere with the operation of the Utopia Level 2 Interface. It can be left unconnected if necessary for a given application. This signal is described in more detail in the NIF chapter of this document. Features of MPHY Layer Cell-Level Handshake (Rx Direction):
s
RxAddr lines.
s
A single MPHY port at a time is selected for a cell transmission. However, another MPHY port may be polled for its RxClav status while the selected MPHY port transfers data. The ATM layer polls the RxClav status of a MPHY port by placing its address on RxAddr. The MPHY port (STLC1510 device) drives RxClav during each cycle following one with its address on the
The ATM selects an MPHY port for transfer by placing the desired MPHY port address onto RxAddr, when RxEnb is deasserted (high) during the current clock cycle and asserted (low) during the following clock cycle. All MPHY devices examine the value on RxAddr for selection purposes when RxEnb is deasserted (high). The MPHY port is selected starting from the cycle after its address is on the RxAddr lines, and RxEnb is deasserted (low); and ending in the cycle a new MPHY port is addressed for selection, and RxEnb is deasserted (high).
Figure 24. illustrates the timing diagram of the receive interface when a cell is received from PHY N and the other PHYs are polled.
Figure 24. UTOPIA Level 2 receive timing, polling phase and selection phase.
se le c tio n
polling
pollin g
Rx C lk
R x A d dr
1F
N -1
1F
N +3
1F
N +1
1F
N N
1F
N+3
1F
N +1
1F
N -1
N +3
N +3 N +1
R x C lav R x E nb
P40 P41
N -1
N +1
P42
P43
P44
P45
P46
P47
P48
H1
H2
H3
H4
U R x D ata
R xSO C
C ell tran sm iss io n from : P H Y N
P H Y N +3
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STLC1510
Figure 25. HPI Block Diagram 8.3 Host Processor Interface (HPI)
A host processor interface is provided to allow the STLC1510 to be controlled by an external microcontroller. The design has been optimized for the Motorola MPC850. More details are provided in the EPM section of this document.
A RM 2H P _IN T H P I_C S N
S T LC 1 5 1 0
HPI
H P I_RW N H P I_A S N H P I_A D D R[2:0 ] H P I_D ATA [7:0] H P I_C LK
Extern al Ho st Pro cess or
Figure 26. Host Processor Interface Timing Diagram
0ns
2 5n s
5 0 ns
75 ns
10 0 ns
RE AD H PI_ C LK a ddr_ su H PI_Addr [2:0] csn_ su H PI_C SN a sn_ su H PI_ AS N rw n_ su HP I_R W N
W R ITE
tw rd at_va lid H PI_D ata [7:0]
tda t_su trw n_ da t_hz
tdat_ h
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STLC1510
8.4 AFE Interface
The interface to the companion Analog Front-end device (STLC1511) operates at a rate of 35.328MHz. It consists of two types:
s s
A serial signal interface for transferring DAC and ADC samples to and from the Aloha ASIC ASIC. A serial control interface for Aloha ASIC.
s
A dual serial pin input pin for ADC samples (RxSIN); * It can carry up to 16 bits. The exact number of bits carried is programmable between 12 and 16. Refer to the AFE interface definition for details. A dual serial pin output pin for DAC samples (TxSOUT); It can carry up to 16 bits. The exact number of bits carried is programmable between 14 and 16. Refer to the AFE interface definition for details An ADC and DAC sample clock input (A_SCLK). For TX and RX interface, data is sent on positive edge of clock and sampled by the receiver on the negative edge of the clock.
s
s
The serial signal interface to the Aloha ASIC provides for transport of transmit and receive data between the LAVA ASIC and Aloha ASIC. This is accomplished with a two bit wide data stream in each direction plus the appropriate clocks. Refer to Figure 27. for the timing diagram of this interface. The serial signal interface consists of six pins:
s
s
s
A 35.328MHz continuous clock output (CK35M);
Figure 27. AFE ADC/DAC Sample Serial Interface Timing Diagram
C K3 5 M
A _SC LK
T xS O U T [0]
a7
a6
a5
a4
a3
a2
a1
a0
T xS O U T [1]
a 15
a1 4
a 13
a 12
a 11
a1 0
a9
a8
R xS IN [0]
b7
b6
b5
b4
b3
b2
b1
b0
R xSIN [ 1]
b 15
b 14
b1 3
b 12
b 11
b10
b9
b8
The serial control I/F consists of 4 pins:
s
The format for the serial interface is given below:
s
SPI_CLK: a gated 35.328MHz clock.It is only present during digital I/F read/write cycles and is inactive otherwise. SPI_ENB: an active low enable pin which allows selection between different AFEs if required. SPI_DTX: an output data pin which is used to send control information to the AFE ASIC. SPI_DRX: an input data pin which is used receive control information from the AFE ASIC. It is enabled only when R/W is low.
s
s
s
s
R/W - determines the access mode for the register address[b1:b0]. ADDR[b2:b0] - identifies the control register accessed. These registers will correspond to the mapping in the LAVA ASIC. WR_DATA[b7:b0] - the control data written to the AFE ASIC.
s
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STLC1510
Figure 28. AFE Control Interface Timing Diagram
S P I_ C L K ( 35M H z)
S P I_ E N B
S P I_ D T X
R /W
A D D R E SS [b2:b 0]
W R _ D A TA { b 7 : b0 ]
S P I_ D R X
R D _ D ATA {b 7 :b 0 ]
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STLC1510
mm DIM. MIN. A A1 A2 b D D1 E E1 e f ddd 0.720 0.650 11.75 0.450 11.75 1.210 0.270 1.120 0.500 12.00 10.40 12.00 10.40 0.800 0.800 0.880 0.950 0.120 0.028 0.025 12.15 0.462 0.550 12.15 0.018 0.462 TYP. MAX. 1.700 MIN. 0.047 0.010
inch TYP. MAX. 0.067
OUTLINE AND MECHANICAL DATA
0.044 0.02 0.472 0.409 0.472 0.409 0.031 0.031 0.034 0.037 0.004 0.478 0.021 0.478
Body: 12 x 12 x 1.7mm
LFBGA132
D D1 e f A2
SETING C PLANE
P N M L K J H G F E D C B A 12 34 5 6 7 8 9 10 11 12 13 14
f E1 e
E
A1 A
A1 CORNER INDEX AREA (SEE NOTE.3)
b (132 BALLS) BOTTOM VIEW
ddd
C
7146828
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STLC1510
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com
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